00001 #ifndef INCL_DEC21041_H_GUARD 00002 #define INCL_DEC21041_H_GUARD 00003 /* 00004 de.h 00005 00006 Header for the driver of the DEC 21140A ethernet card as emulated 00007 by VirtualPC 2007 00008 00009 Created: 09/01/2009 Nicolas Tittley (first.last @ gmail DOT com) 00010 */ 00011 00012 00013 #define DE_PORT_NR 1 00014 00015 #define DE_FKEY 8 /* Shitf+ this value will dump info on console */ 00016 00017 #undef NULL 00018 #define NULL ((void *)0) 00019 #define NOT(x) (~(x)) 00020 00021 #if debug == 1 00022 # define DEBUG(statm) statm 00023 #else 00024 # define DEBUG(statm) 00025 #endif 00026 00027 00028 #define SA_ADDR_LEN sizeof(ether_addr_t) 00029 00030 #define DE_NB_SEND_DESCR 32 00031 #define DE_SEND_BUF_SIZE (ETH_MAX_PACK_SIZE+2) 00032 #define DE_NB_RECV_DESCR 32 00033 #define DE_RECV_BUF_SIZE (ETH_MAX_PACK_SIZE+2) 00034 #define IOVEC_NR 16 00035 #define DE_MIN_BASE_ADDR 0x0400 00036 #define DE_SROM_EA_OFFSET 20 00037 #define DE_SETUP_FRAME_SIZE 192 00038 #define DEC21140A_VID 0x1011 00039 #define DEC21140A_DID 0x0009 00040 00041 00042 typedef struct iovec_dat_s { 00043 iovec_s_t iod_iovec[IOVEC_NR]; 00044 int iod_iovec_s; 00045 int iod_proc_nr; 00046 cp_grant_id_t iod_grant; 00047 vir_bytes iod_iovec_offset; 00048 } iovec_dat_s_t; 00049 00050 typedef struct de_descr { 00051 u32_t des[4]; 00052 } de_descr_t; 00053 00054 typedef struct de_local_descr { 00055 de_descr_t *descr; 00056 u8_t *buf1; 00057 u8_t *buf2; 00058 } de_loc_descr_t; 00059 00060 typedef struct dpeth { 00061 00062 message rx_return_msg; /* Holds VREAD message until int */ 00063 message tx_return_msg; /* Holds VWRITE message until int */ 00064 char de_name[32]; /* Name of this interface */ 00065 port_t de_base_port; /* Base port, for multiple card instance */ 00066 int de_irq; /* IRQ line number */ 00067 int de_hook; /* interrupt hook at kernel */ 00068 00069 int de_type; /* What kind of hardware */ 00070 00071 ether_addr_t de_address; /* Ethernet Address */ 00072 eth_stat_t de_stat; /* Stats */ 00073 unsigned long bytes_tx; /* Number of bytes sent */ 00074 unsigned long bytes_rx; /* Number of bytes recv */ 00075 00076 /* Space reservation. We will allocate all structures later in the code. 00077 here we just make sure we have the space we need at compile time */ 00078 u8_t sendrecv_descr_buf[(DE_NB_SEND_DESCR+DE_NB_RECV_DESCR)* 00079 sizeof(de_descr_t)]; 00080 u8_t sendrecv_buf[DE_NB_SEND_DESCR*DE_SEND_BUF_SIZE + 00081 DE_NB_RECV_DESCR*DE_RECV_BUF_SIZE]; 00082 phys_bytes sendrecv_descr_phys_addr[2]; 00083 de_loc_descr_t descr[2][MAX(DE_NB_RECV_DESCR, DE_NB_SEND_DESCR)]; 00084 int cur_descr[2]; 00085 00086 #define DESCR_RECV 0 00087 #define DESCR_TRAN 1 00088 00089 int de_flags; /* Send/Receive mode (Configuration) */ 00090 00091 #define DEF_EMPTY 0x0000 00092 #define DEF_READING 0x0001 00093 #define DEF_RECV_BUSY 0x0002 00094 #define DEF_ACK_RECV 0x0004 00095 #define DEF_SENDING 0x0010 00096 #define DEF_XMIT_BUSY 0x0020 00097 #define DEF_ACK_SEND 0x0040 00098 #define DEF_PROMISC 0x0100 00099 #define DEF_MULTI 0x0200 00100 #define DEF_BROAD 0x0400 00101 #define DEF_ENABLED 0x2000 00102 #define DEF_STOPPED 0x4000 00103 00104 int de_mode; /* Status of the Interface */ 00105 00106 #define DEM_DISABLED 0x0000 00107 #define DEM_SINK 0x0001 00108 #define DEM_ENABLED 0x0002 00109 00110 00111 /* Serial ROM */ 00112 #define SROM_BITWIDTH 6 00113 00114 u8_t srom[((1<<SROM_BITWIDTH)-1)*2]; /* Space to read in 00115 all the configuration ROM */ 00116 00117 00118 /* Temporary storage for RECV/SEND requests */ 00119 iovec_dat_s_t de_read_iovec; 00120 iovec_dat_s_t de_write_iovec; 00121 vir_bytes de_read_s; 00122 vir_bytes de_send_s; 00123 int de_client; 00124 00125 } dpeth_t; 00126 00127 00128 /************/ 00129 /* Revisons */ 00130 /************/ 00131 00132 #define DEC_21140A 0x20 00133 #define DE_TYPE_UNKNOWN 0x0 00134 /* #define CSR_ADDR(x, i) csraddr2(x->de_base_port + i) */ 00135 #define CSR_ADDR(x, i) (x->de_base_port + i) 00136 00137 /* CSRs */ 00138 #define CSR0 0x00 00139 #define CSR0_SWR 0x00000001 /* sw reset */ 00140 #define CSR0_BAR 0x00000002 /* bus arbitration */ 00141 #define CSR0_CAL_8 0x00004000 /* cache align 8 long word */ 00142 #define CSR0_TAP 0x00080000 /* trans auto polling */ 00143 #define CSR1 0x08 /* transmit poll demand */ 00144 #define CSR2 0x10 /* receive poll demand */ 00145 #define CSR3 0x18 /* receive list address */ 00146 #define CSR4 0x20 /* transmit list address */ 00147 #define CSR5 0x28 /* status register */ 00148 #define CSR5_EB 0x03800000 /* error bits */ 00149 #define CSR5_TS 0x00700000 /* Transmit proc state */ 00150 #define CSR5_RS 0x000E0000 /* Receive proc state */ 00151 #define CSR5_NIS 0x00010000 /* Norm Int summ */ 00152 #define CSR5_AIS 0x00008000 /* Abnorm Int sum */ 00153 #define CSR5_FBE 0x00002000 /* Fatal bit error */ 00154 #define CSR5_GTE 0x00000800 /* Gen-purp timer exp */ 00155 #define CSR5_ETI 0x00000400 /* Early Trans int */ 00156 #define CSR5_RWT 0x00000200 /* Recv watchdog timeout */ 00157 #define CSR5_RPS 0x00000100 /* Recv proc stop */ 00158 #define CSR5_RU 0x00000080 /* Recv buf unavail */ 00159 #define CSR5_RI 0x00000040 /* Recv interrupt */ 00160 #define CSR5_UNF 0x00000020 /* Trans underflow */ 00161 #define CSR5_TJT 0x00000008 /* Trans Jabber Timeout */ 00162 #define CSR5_TU 0x00000004 /* Trans buf unavail */ 00163 #define CSR5_TPS 0x00000002 /* Trans proc stopped */ 00164 #define CSR5_TI 0x00000001 /* Trans interrupt */ 00165 #define CSR6 0x30 /* Operation mode */ 00166 #define CSR6_SC 0x80000000 /* Special capt effect ena 31 */ 00167 #define CSR6_RA 0x40000000 /* receive all 30 */ 00168 #define CSR6_MBO 0x02000000 /* must be one 25 */ 00169 #define CSR6_SCR 0x01000000 /* Scrambler mode 24 */ 00170 #define CSR6_PCS 0x00800000 /* PCS function 23 */ 00171 #define CSR6_TTM 0x00400000 /* Trans threshold mode 22 */ 00172 #define CSR6_SF 0x00200000 /* store and forward 21 */ 00173 #define CSR6_HBD 0x00080000 /* Heartbeat disable 19 */ 00174 #define CSR6_PS 0x00040000 /* port select 18 */ 00175 #define CSR6_CA 0x00020000 /* Capt effect ena 17 */ 00176 #define CSR6_TR_00 0x00000000 /* Trans thresh 15:14 */ 00177 #define CSR6_TR_01 0x00004000 /* Trans thresh 15:14 */ 00178 #define CSR6_TR_10 0x00008000 /* Trans thresh 15:14 */ 00179 #define CSR6_TR_11 0x0000C000 /* Trans thresh 15:14 */ 00180 #define CSR6_ST 0x00002000 /* start/stop trans 13 */ 00181 #define CSR6_FD 0x00000200 /* Full Duplex 9 */ 00182 #define CSR6_PM 0x00000080 /* Pass all multicast 7 */ 00183 #define CSR6_PR 0x00000040 /* Promisc mode 6 */ 00184 #define CSR6_IF 0x00000010 /* Inv filtering 4 */ 00185 #define CSR6_HO 0x00000004 /* Hash-only filtering 2 */ 00186 #define CSR6_SR 0x00000002 /* start/stop recv 1 */ 00187 #define CSR6_HP 0x00000001 /* Hash/perfect recv filt mode 0 */ 00188 #define CSR7 0x38 /* Interrupt enable */ 00189 #define CSR7_NI 0x00010000 /* Normal interrupt ena */ 00190 #define CSR7_AI 0x00008000 /* Abnormal int ena */ 00191 #define CSR7_TI 0x00000001 /* trans int ena */ 00192 #define CSR7_TU 0x00000004 /* trans buf unavail ena */ 00193 #define CSR7_RI 0x00000040 /* recv interp ena */ 00194 #define CSR7_GPT 0x00000800 /* gen purpose timer ena */ 00195 #define CSR9 0x48 /* Boot Rom, serial ROM, MII */ 00196 #define CSR9_SR 0x0800 /* serial ROM select */ 00197 #define CSR9_RD 0x4000 /* read */ 00198 #define CSR9_DO 0x0008 /* data out */ 00199 #define CSR9_DI 0x0004 /* data in */ 00200 #define CSR9_SRC 0x0002 /* serial clock */ 00201 #define CSR9_CS 0x0001 /* serial rom chip select */ 00202 /* Send/Recv Descriptors */ 00203 00204 #define DES0 0 00205 #define DES0_OWN 0x80000000 /* descr ownership. 1=211140A */ 00206 #define DES0_FL 0x3FFF0000 /* frame length */ 00207 #define DES0_FL_SHIFT 16 /* shift to fix frame length */ 00208 #define DES0_ES 0x00008000 /* Error sum */ 00209 #define DES0_TO 0x00004000 /* Trans jabber timeout */ 00210 #define DES0_LO 0x00000800 /* Loss of carrier */ 00211 #define DES0_NC 0x00000400 /* no carrier */ 00212 #define DES0_LC 0x00000200 /* Late coll */ 00213 #define DES0_EC 0x00000100 /* Excessive coll */ 00214 #define DES0_UF 0x00000002 /* Underflow error */ 00215 #define DES0_RE 0x00000008 /* MII error */ 00216 #define DES0_FS 0x00000200 /* first descr */ 00217 #define DES0_LS 0x00000100 /* last descr */ 00218 #define DES1 1 00219 #define DES1_ER 0x02000000 /* end of ring */ 00220 #define DES1_SAC 0x01000000 /* 2nd address chained */ 00221 #define DES1_BS2 0x003FF800 /* 2nd buffer size */ 00222 #define DES1_BS2_SHFT 11 /* shift to obtain 2nd buffer size */ 00223 #define DES1_BS1 0x000007FF /* 1nd buffer size */ 00224 #define DES1_IC 0x80000000 /* Interrupt on completion 31 */ 00225 #define DES1_LS 0x40000000 /* Last Segment 30 */ 00226 #define DES1_FS 0x20000000 /* First Segment 29 */ 00227 #define DES1_FT1 0x10000000 /* Filtering type 28 */ 00228 #define DES1_SET 0x08000000 /* Setup frame 27 */ 00229 #define DES1_AC 0x04000000 /* Add CRC disable 26 */ 00230 #define DES1_DPD 0x00800000 /* Disabled padding 23 */ 00231 #define DES1_FT0 0x00400000 /* Filtering type 22 */ 00232 #define DES2 2 /* 1st buffer addr */ 00233 #define DES3 3 /* 2nd buffer addr */ 00234 00235 #define DES_BUF1 DES2 00236 #define DES_BUF2 DES3 00237 00238 #endif /* Include Guard */
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